Transient and intermittent faults in storage circuits (e.g., RAM, registers, etc.) may cause errors during the execution of programs when affected values read from the storage circuits are used to perform computations. Existing error handling techniques use parity or error correction code (ECC) checking to detect that a value read from a storage circuit is not correct. When an error is detected, a retry (if possible) may be initiated or the operation may be stopped and the error may be flagged.
More recently, errors are caused when supply voltages are reduced to lower the power consumption of a circuit. An example of error-handling for errors resulting from reductions in supply voltage levels is a word masking and bit masking technique disclosed in “Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators” by Reagen et al., that uses a razor circuit to determine if a weight value read out of an SRAM has an error. When the razor circuit indicates the weight value has an error, a zero is substituted for the weight value (i.e., word masking) or the sign bit of the weight value is substituted for any incorrect bits (i.e., bit masking). Substituting a zero allows the computation to continue, and typically reduces the amount of the error in the final result. Razor circuits are included for each column of the SRAM to detect an error in any bit that is read from the SRAM. The razor circuits increase the power consumption and die area of the SRAM and do not correct the errors that are detected. Additional circuitry is needed to correct the errors. There is a need for addressing these issues and/or other issues associated with the prior art.